Not applicable.
Not applicable.
1. Field of the Invention
The present invention relates generally to the field of digital video compression and particularly to memory arbitration within a digital video decoder. More particularly, the present invention relates to a video decoder including a memory arbitration scheme that combines the advantages of hardware-based memory arbitration with the advantages of software-based memory arbitration.
2. Background of the Invention
Real-time processing of full motion video sequences using a digital recording, playback, or transmission system requires a large number of numerical computations and data transactions in a relatively short amount of time. Motion pictures typically are constructed using multiple still pictures which are displayed one at a time in sequence. To record the video sequence, each still picture, or xe2x80x9cframe,xe2x80x9d must be digitally mapped onto a rectangular grid of pixels, each pixel representing the light intensity and color for a portion of the frame. In a Red-Green-Blue (RGB) system, each pixel includes three parameters which denote the intensity of the red, green, and blue light components, respectively, of that pixel. In accordance with the system defined by the National Television Standards Committee (NTSC), pixel data may also be described by a luminance parameter, which denotes the light intensity of the pixel, and two chrominance parameters, which describe the color of the pixel.
Although these systems specify only three parameters to describe each pixel, multiple frames must be displayed every second, each frame comprising hundreds of thousands of pixels if displayed on a typical computer monitor or television screen. In addition, it is usually desirable to include other multimedia information such as audio data along with the pixel data. As a result, a typical motion picture may involve many millions of data values that must be processed, stored, or transmitted each second. Because of the difficulty of building systems that can transmit and store audio and video data affordably at such high rates, various types of data compression algorithms have been introduced which allow the motion picture frames to be represented using a reduced amount of data. Video and audio systems which use these compression techniques require less storage space and transmission bandwidth, reducing the overall cost of the systems.
Video compression algorithms employ a number of techniques. Intraframe compression techniques seek to reduce the amount of data needed to describe a single picture frame, while interframe compression techniques reduce the amount of data needed to describe a sequence of pictures by exploiting redundancies between frames. The discrete cosine transform (DCT), used for interframe compression, is a mathematical process for determining a set of coefficients that describe the frequency characteristics of the pixels in a given picture frame. Because DCT coefficients can be converted back to pixel values using a mathematical process known as the Inverse DCT (IDCT), it is common in the art to represent frame data using DCT coefficients instead of the actual pixel values. Because the human eye is more responsive to lower frequencies in an image than to higher frequencies in a picture, a certain amount of high frequency picture information can be discarded or reduced without noticeably affecting the visual quality of a given frame. Once the DCT coefficients are determined, high frequency coefficients also can be quantized, a method which reduces the number of binary digits (or xe2x80x9cbitsxe2x80x9d) required to represent the coefficient values. Reducing the amount of high frequency information and/or quantizing the high frequency coefficients compresses the picture, reducing the amount of data needed to process, store, and transmit the picture.
Other intraframe compression techniques include run level encoding (RLE), zigzag ordering, and variable length encoding. Run-level encoding expresses a data sequence in terms of ordered pairs that consists of a number of zeroes between nonzero coefficients, and the value of the nonzero coefficient that terminates the run of zeroes. Zigzag ordering arranges the DCT components according to frequency, so that coefficients representing similar frequencies are stored and transmitted together. Zigzag ordering increases the effectiveness of the RLE technique, since some frequency components, especially high frequency components, tend to have numerous zero values. Variable length coding allows the data values to be represented using codewords which require, on average, fewer bits than the data values themselves. As a result, variable-length codes can be used to reduce the amount of storage space and transmission bandwidth required by the system. Some examples of video data compression formats are the Joint Photographic Experts Group (JPEG) format and the Graphic Interchange Format (GIF). It should be noted that compression techniques may be classified as either lossless (no image degradation) or lossy (some image degradation and that some compression formats are capable of producing a wide range of image qualities, varying from no degradation (lossless) to moderate or extreme degradation (lossy). For more information on coding, refer to Digital Communications by Proakis (McGraw-Hill, 1995) or Elements of Information Theory by Cover and Thomas (John Wiley and Sons, 1991).
Interframe compression techniques exploit redundancies between consecutive video frames, known as temporal redundancies. Because moving pictures often involve either very little motion or motion primarily of foreground objects, consecutive frames often are highly similar, increasing the effectiveness of interframe compression. Interframe compression generally involves storing the differences between successive frames in the data file instead of the actual frame data itself. Interframe compression begins by storing the entire image of a reference frame, generally in a moderately compressed format. Successive frames are compared with the reference frame, and only the differences between the reference frame and the successive frames are stored. Periodically, such as when new scenes are displayed, new reference frames are stored, and subsequent comparisons begin from this new reference point. The level of interframe compression achieved, known as the compression ratio, may be content-dependent; i.e., if the video clip includes many abrupt scene transitions from one image to another, the compression is less efficient. It is noted that the interframe compression ratio may be held constant while varying the video quality, however. Examples of names video compression techniques which use interframe compression are MPEG, DVI, and Indeo, among others. Using known techniques, the interframe-compressed pictures can be later reconstructed by a video decoder.
The International Organization for Standardization (ISO) has developed a number of compression standards for audio/video systems, namely the Motion Pictures Experts Group (MPEG) standards, which include MPEG-1 and MPEG-2. The ISO publishes the MPEG standards under the official name of ISO/IEC JTC1 SC29 WG11. The MPEG-1 standard defines data reduction techniques that include block-based motion compensation prediction (MCP), which generally involves differential pulse code modulation (DPCM). The MPEG-2 standard is similar to the MPEG-1 standard but includes extensions to cover a wider range of applications, including interlaced digital video such as high definition television (HDTV).
An MPEG data stream includes three types of pictures, referred to as the Intraframe (or xe2x80x9cI-framexe2x80x9d), the Predicted frame (or xe2x80x9cP-framexe2x80x9d), and the Bi-directional Interpolated frame (or xe2x80x9cB-framexe2x80x9d). The I-frames contain the video data for an entire frame of video and are typically placed every 10 to 15 frames. Intraframes generally are only moderately compressed. Predicted frames are encoded with reference to a past frame, i.e., a prior Intraframe or Predicted frame. Thus P-frames only include changes relative to prior I-frames or P-frames. In general, P-frames receive a fairly high amount of compression and are used as references for future P-frames. Thus, both I- and P-frames are used as references for subsequent frames. Bi-directional pictures include the greatest amount of compression and require both a past and a future reference in order to be encoded. Bi-directional frames are never used as references for other frames.
Typically, as for the frame(s) following a reference frame (i.e., P-frames and B-frames), only small portions of these frames are different from the corresponding portions of the respective reference frame. Thus, for these frames, only the differences between frames are captured, compressed and stored.
When an MPEG encoder receives a video file or bitstream, the MPEG encoder generally first creates the I-frames. The MPEG encoder may compress the I-frame using an intraframe lossless compression technique. After the I-frames have been created, the MPEG encoder divides subsequent frames into a grid of 16xc3x9716 pixel squares called macroblocks, in order to perform motion estimation and compensation. The encoder searches for a best fit or best match between the target picture macroblock, i.e., the macroblock being encoded, and a block in one or more reference frames. For a target P-frame, the encoder searches in prior I-frames or P-frames. For a target B-frame, the encoder searches in a prior and subsequent I-frame or P-frame. When a best match to the target macroblock is found, the encoder encodes a vector movement code, or motion vector. The motion vector includes a pointer to the best fit reference frame block as well as information on the difference between the best fit block and the respective target block. The blocks in target pictures that have no change relative to the corresponding blocks in the reference frame are ignored. Thus the amount of data that is actually stored for these frames is significantly reduced.
After motion vectors have been generated, the encoder encodes the difference between corresponding macroblocks. Because human perception is more sensitive to brightness changes than color changes, the MPEG algorithm devotes more effort to reducing color space rather than brightness. Thus, each macroblock is divided into four 8xc3x978 sub-blocks representing the brightness and two 8xc3x978 sub-blocks representing the color. In order to represent all 256 pixels using only two 8xc3x978 sub-blocks, the macroblocks are subsampled so that each pixel in a sub-block represents multiple pixels in the macroblock.
Once the I-frames, P-frames, and B-frames have been constructed to represent the video sequence with temporal compression, each frame may be further compressed individually. First, using the DCT, each sub-block is converted from a set of pixel values to the frequency domain. Each DCT coefficient is then quantized according to a set of predetermined quantization tables. The quantization step for each frequency can vary, taking into account the sensitivity of the human visual system (HVS) to the frequency. Since the HVS is more sensitive to low frequencies, many of the high frequency coefficients are coarsely quantized, resulting in some lost information. The DCT coefficients are reordered using a zigzag pattern and then run-level encoded. Because the high-frequency coefficients are more likely to be zero, run-level coding results in additional video compression. The video encoder then performs variable-length coding (VLC) on the run-level pairs. VLC is a reversible procedure for coding data that assigns shorter code words to frequent events and longer code words to less frequent events, thereby achieving additional video compression. Huffman encoding is a particularly well-known form of variable length coding.
The compressed video data then is ready to be transmitted to a remote location or stored for future decoding. In a live teleconferencing system, for instance, the compressed data is transmitted to a remote receiver which decodes the compressed bitstream for viewing. The video data may also be stored into a computer file for later retrieval or pressed onto a CD ROM or Digital Versatile Disk (DVD) for distribution or storage.
The MPEG-2 data format organizes the compressed bitstream into several syntax layers which identify specific portions of the video data. The outermost layer is called the Sequence (SEQ) Layer and simply identifies a sequence of related pictures comprising a movie or a portion of a movie. The Group of Pictures (GOP) Layer lies beneath the Sequence Layer. Each Group of Pictures contains one I-frame and multiple P-frames and B-frames. Further, there are two types of GOP Layers: open and closed. In a closed GOP Layer, the P-frames within a given GOP Layer are derived entirely from the I-frame in that GOP, while the B-frames within that layer are derived entirely from the I-frame and/or P-frames in that GOP. Thus, a closed Group of Pictures is self-sufficient in that the video frames within that GOP can be decoded using only the information within that GOP. In an open GOP Layer, the B-frames in the beginning of the layer may be encoded based on anchor frames in previous GOP layers. The Picture (PICT) Layer identifies a single frame of video and can hold any type of frame, an I-frame, P-frame, or B-frame. Below the Picture Layer is the Slice Layer, which represents a series of an arbitrary number of consecutive macroblocks. A slice may vary in size, although the first and last macroblock of a slice shall be in the same horizontal row of macroblocks. Hence, the minimum slice has a single macroblock, and the maximum slice includes an entire macroblock row from the video frame. Each slice is divided into macroblocks, which are grids of pixels having 256 elements organized into 16 rows and 16 columns. It follows that each slice comprises one or more rows of macroblocks. The Macroblock (MB) Layer further can be divided into the Block Layer, each block representing an 8xc3x978 grid of pixels. Table I summarizes the layering format of the MPEG-2 bitstream.
The composition of the MPEG-2 bitstream includes headers to denote the beginning of each layer. The header may contain specific information about the video sequence, such as the frame rate, or may even include video data, such as the motion vectors included within macroblock headers.
The video decoding process, employed to reconstruct a motion picture sequence from a compressed and encoded bitstream, generally is the inverse of the video encoding process. The decoder must first identify the beginning of a coded picture, identify the type of picture, then decode each individual macroblock within a particular picture. When encoded video data is transferred to a video decoder, the encoded video data is received and stored in a rate or channel buffer. The data is then retrieved from the channel buffer by a decoder or reconstruction device for performing the decoding process. When the MPEG decoder receives the encoded stream, the MPEG decoder reverses the above operations. Thus the MPEG decoder performs variable length decoding and inverse RLE, inverse scanning to remove the zigzag ordering, inverse quantization to de-quantize the data, and the inverse DCT to convert the data from the frequency domain back to the pixel domain. The MPEG decoder also performs motion compensation using the transmitted motion vectors to re-create the temporally compressed frames.
Reference frames, i.e., I-frames or P-frames, are decoded and stored into a frame buffer. Temporally compressed or encoded frames, such as P-frames or B-frames, are target frames and include motion vectors that point to reference blocks in neighboring I-frames or P-frames stored in the frame buffer. The neighboring I-frames or P-frames are known as anchor frames, since the target frames are decoded based on the anchor frames. The MPEG decoder locates the reference block in the anchor frame, as specified by the motion vector, and reconstructs the target macroblock by combining the reference macroblock with the pixel values for the target macroblock.
In order to reconstruct a B-frame, the two related anchor frames or reference frames must be decoded and available in a memory, referred to as the picture buffer. This is necessary since the B-frame was encoded relative to these two anchor frames. Thus the B-frame must be interpolated, or reconstructed, using both anchor frames during the reconstruction process.
As described above, as the encoded video data is decoded, the decoded data is stored into a frame buffer. In some configurations, the channel and frame buffers are incorporated into a single integrated memory buffer. The decoded data is in the form of decompressed or decoded I-frames, P-frames, or B-frames. A display processor retrieves the picture data for display by an appropriate display device, such as a TV monitor or the like.
FIG. 1 illustrates an exemplary MPEG-2 decoder 100 which includes a variable length decoder (VLD) 102 coupled to a microcontroller 104, a memory controller 120, a pipeline unit 116, and an audio decoder 108. Memory controller 120 further couples to pipeline 116, a display controller 112, and a main memory device 128, such as a dynamic random access memory (DRAM) or a synchronous DRAM (SDRAM). The memory controller 120 includes a memory arbiter 124 which receives memory transactions from various devices within the decoder 100. FIG. 1 shows various devices connected to the arbiter 124 via READ signals for receiving data from the main memory 128 and via WRITE signals for storing data in memory. Accordingly, VLD 102 couples to the memory controller 120 via WRITE 132 and READ 136 signals, pipeline 116 couples to the memory controller 120 via WRITE 140 and READ 144 signals, and the display controller 112 couples to the memory controller 120 via READ signals 148. The decoder 100 may include other devices capable of read and write transactions with memory, as well. The arbiter 124 serves as a gateway to memory 128 by granting one memory request at a time.
The overall decoding process typically is controlled by the microcontroller 104, which asserts control signals (not shown) to the various data processing devices within decoder 100, such as the VLD 102, pipeline 116, audio decoder 108, and display controller 112. The control signals instructs these data processing devices, 102, 108, 116, and 112, when to process incoming data. The microcontroller thus controls the decoding process by asserting control signals to the data processing devices in the proper order. The microcontroller 104 further may receive status and handshaking signals from the data processing devices which indicate the status of those devices.
The VLD 102 parses the incoming compressed bitstream, routing the coded information to a portion of main memory 120 reserved for the channel buffer. The incoming bitstream may or may not be synchronized with the frames that are being decoded, i.e., frames in the bitstream may be stored into the channel buffer at an irregular rate. The VLD 102 next performs post-parsing, reading the compressed data from the channel buffer and decompressing the zigzag ordered, RLE/variable length encoded bitstream. The decompressed frame data, which includes DCT frequency coefficients and motion vectors, is transmitted to the pipeline 116 along with certain header data that allows the pipeline 116 to properly reconstruct the video frames. Header and control information typically is routed to the microcontroller 104, while audio data packets are routed to the audio decoder 108. The audio decoder 108 decodes the sound information independently from the video processing and provides an AUDIO OUT signal.
The pipeline 116 typically includes such circuitry as an inverse discrete cosine transform (IDCT) unit, a motion compensation (MC) unit, and a merge and store (MS) unit, which decode the compressed macroblocks using the DCT coefficients and motion compensation vectors. The pipeline unit 116 writes decoded frames into the frame buffer, from which the pipeline unit 116 may also access previously decoded I-frames and P-frames when decoding subsequent P-frames or B-frames.
The display controller 112 reads the pixel data for each frame from the frame buffer, providing a VIDEO OUT signal suitable for a display device. The display controller provides the video frames at regular time intervals according to a specific frame rate defined in the bitstream.
Because of the large number of memory accesses handled by the main memory 128, the arbiter 124 must be able to efficiently and fairly distribute grants for memory access between the VLD 102, pipeline 116, display controller 112, and any other device requesting memory access. Failure to timely grant certain memory requests may result in corrupted video output. For instance, the display controller 112 is required to transmit a frame of video within a fixed time interval. If a memory request by the display controller 112 is not met in time, then the display controller 112 will have no data to transmit, and the video sequence will appear corrupted. Similarly, if memory requests by the pipeline 116 are not met in time, then the video frames might not be decoded in time to be retrieved and displayed by the display controller 112. It is also important that the VLD 102 be given sufficient access to memory to allow the bitstream data to be captured and transmitted to the microcontroller 104, audio decoder 108, and pipeline 116. Due to the fact that all data processing within the decoder 100 must occur in real time, it is important that the arbiter 124 give each data processing device sufficient and timely memory. access.
The MPEG bitstream may vary greatly from one video sequence to the next and even between different parts of a given movie, however. For instance, the variable length coding process may provide better compression for some frame sequences than others, and some video frames may therefore require more or less decoding by the VLD 102 than do other frames. Similarly, some action sequences may require heavier DCT and motion vector processing, and the arbiter 124 must allow the pipeline 116 sufficient access to the frame buffer to decode the fast sequences without memory-starving the VLD 102 or display controller 112. As a result, the relative demands placed on the arbiter 124 by the VLD 102 and pipeline 116 may vary throughout the decoding process. Although memory arbiters have been designed that can efficiently handle numerous memory requests, it is difficult to design a memory arbiter that can dynamically adjust for these variations in memory demand.
FIG. 2 illustrates a similar architecture for an MPEG decoder 200, in which the microcontroller 204 is programmed to handle the memory arbitration. The microcontroller 204 receives status signals (not shown) from the various processing devices that indicate which devices need access to memory. To grant memory accesses, the microcontroller 204 asserts GO signals to the processing devices. In decoder 200, the VLD 202 receives GO signal 203, the pipeline unit 216 receives GO signal 206, and the display controller receives GO signal 208. Because the microcontroller 204 has access to header and control data contained in the bitstream, the microcontroller 204 may dynamically determine an appropriate balance of memory accesses to grant to the various processing devices. The microcontroller 204 then grants memory access to one device at a time by asserting a GO signal to that device. Under such a system, the memory controller 220 receives only one memory request at a time and does not need to arbitrate among memory requests. Further, the balance of memory requests between devices can be optimally adjusted according to the changing nature of the incoming bitstream. In addition, because the microcontroller operates according to internally stored software instructions, the programmer can update the microcontroller firmware at any time in order to improve the arbitration scheme.
One drawback to implementing memory arbitration with software, however, is that the microcontroller may not be capable of responding to memory requests as quickly as a hardware unit such as arbiter 124. A microcontroller typically handles one instruction at a time and loops repeatedly through the instructions. If a processing device transmits a memory request to the microcontroller 204, then the microcontroller 204 must process a string of instructions to determine which device is submitting the request, whether other devices are requesting memory access, whether the memory device is available, and whether the requesting device should receive priority over other devices requesting memory access. Accordingly, a microcontroller 204 often requires numerous processing cycles to grant memory requests and cannot react as quickly as a dedicated hardware device. As a result, it is difficult for a microcontroller-based arbitration scheme to successfully process video sequences with large amounts of data and/or quickly moving objects, also known as xe2x80x9ckiller streams.xe2x80x9d Such streams often appear corrupted onscreen because of the inability of the decoder to process the sheer amount of data in the required time period.
For the foregoing reasons, a memory arbitration scheme which combines the speed and responsiveness of a dedicated hardware arbiter with the flexibility and efficiency of software arbitration would greatly improve video decoder performance. Despite the apparent advantages that such a system would provide, to date, no such device has been developed that provides these features.
Accordingly, there is provided herein a decoding system that uses a memory arbitration scheme that combines the speed and responsiveness of hardware with the flexibility and efficiency of software to improve decoding system performance. In one embodiment, the decoding system is an MPEG decoder that comprises a memory device, a plurality of decoding units coupled to the memory device, and a microcontroller coupled to the memory device and decoding units. The decoder also includes a memory controller for facilitating memory transactions and a sub-picture unit capable of decoding graphic images such as on-screen menus to be combined with the video output. The decoding units, which include an audio unit, a variable length decoder, an IDCT unit, a motion compensation unit, a merge and store unit, and a display controller, generally perform the calculations necessary to decode the incoming video data and are capable of reading and writing from the memory device. The variable length decoder receives the incoming MPEG bitstream, stores the encoded MPEG data into a channel buffer, and decodes the zigzag-ordered, run-level-encoded MPEG data. The variable length decoder then parses the bitstream, transmitting audio packets to the audio unit, headers and control data to the microcontroller, and DCT coefficients to the IDCT unit.
The headers received by the microcontroller include motion vectors, which point to target macroblocks in a previously received target frame in the frame buffer. The microcontroller converts the motion vectors into memory addresses indicating the location of the target macroblocks in the frame buffer. The memory addresses are then transmitted to the motion compensation unit, which retrieves the target macroblocks from main memory. The IDCT unit converts the DCT coefficients into pixel data, which are sent to the merge and store unit. The merge and store unit combines the macroblock retrieved by the motion compensation unit with the pixel data to produce a new macroblock. The new macroblock is then stored into the frame buffer. If the new macroblock is part of an anchor frame, i.e., either an I-frame or a P-frame, then it may be used for decoding a subsequent target frame.
The display controller also couples to the memory device and periodically retrieves decoded video frames from the frame buffer. Based on the decoded frames, the display controller provides a video output signal suitable for a display device. The sub-picture unit retrieves sub-picture packets from main memory which represent bitmap graphics to be superimposed onto the video data. The sub-picture unit decodes the sub-picture packets, transferring the decoded graphics to the display unit. The display unit combines the sub-picture graphics with the video output signal.
The microcontroller manages the decoding units, asserting memory grant signals, or GO signals, to instruct the decoding devices when to operate and thereby when to access memory. The microcontroller thus handles arbitration for the memory device. The microcontroller also provides a GO signal to the memory controller indicating when to run refresh cycles. The memory device can only perform one memory transaction at a time, and the microcontroller must therefore issue only one GO signal one at a time.
Because of the varying nature of video sequences, the relative demand for memory access among the decoding units may change over time. Accordingly, the microcontroller is capable of determining how much memory access each device needs and issuing the GO signals accordingly. As a result, devices that need relatively few memory transactions are given fewer memory access opportunities in order to allow other devices more frequent access to memory. The microcontroller evaluates the bitstream headers to determine the video composition and can tailor the sequence of memory accesses according to the changing nature of the video sequence. By providing a flexible memory arbitration scheme, the decoding devices are better able to handle xe2x80x9ckillerxe2x80x9d data streams than are conventional decoding devices.
In contrast with conventional software-based memory arbitration schemes, the present invention incorporates dedicated logic devices to issue the GO signals for memory access. The microcontroller generally comprises a control logic that receives headers and other bitstream data from the variable length decoder and feeds GO instructions to a first-in, first-out (FIFO) queue, known as the GOFIFO. The control logic also includes circuitry necessary to execute program instructions. Dequeue logic coupled to the GOFIFO unit receives memory ready signals from the decoding units and asserts a DEQUEUE signal if the memory device is idle and therefore ready to handle a memory transaction. If not empty, the GOFIFO dequeues one of the stored GO instructions in response to the DEQUEUE signal. The dequeued GO instruction is fed into a first 2xc3x971 multiplexer, which provides a GO signal permitting one of the decoding units to access memory.
Because the GOFIFO issues the GO signals when the memory device is available, the control logic is allowed to focus on other aspects of the decoding process. Hence, the GOFIFO relieves the control logic from having to monitor the memory device to determine when memory transactions should be initiated. The control logic needs only determine the memory access sequence and queue the GO instructions into the GOFIFO. Because it is freed from processing numerous instruction cycles to monitor memory and initiate the GO signals, the control logic is able to operate more efficiently. Also, the GOFIFO and dequeue unit inherently are able to issue GO instructions faster than the control logic, since the GOFIFO is hardwired and does not have to execute a string of software instructions to operate. As a result, memory transactions can occur back-to-back with negligible delay, using the available memory bandwidth more efficiently.
The microcontroller circuit also includes a default GO unit for providing default memory grant signals when the GOFIFO is empty. The default GO unit receives the DEQUEUE signal from the dequeue logic and the FIFO_EMPTY signal from the GOFIFO. If the GOFIFO is empty, then the default GO logic asserts a GO signal in response to the DEQUEUE signal. The default GO unit provides a different GO signal each time, rotating through a subset of the GO signals that are available to the GOFIFO. In the preferred embodiment, the default GO unit is capable of providing GO signals for the variable length decoder, the display controller, and refresh cycle when the GOFIFO is empty. A second 2xc3x971 multiplexer disposed between the GOFIFO and first 2xc3x971 multiplexer receives GO signals from both the GOFIFO and the default GO unit. If the FIFO_EMPTY signal indicates that the GOFIFO is currently empty, then the second multiplexer selects a GO signal from the default GO unit. The second multiplexer selects a GO signal from the GOFIFO if the GOFIFO_EMPTY signal is deasserted, however. Because the default GO unit can provide GO signals for the variable length decoder, display controller, and refresh cycle, the MPEG decoder is capable of providing basic parsing and display functions and retaining the memory contents even if the control logic does not issue a GO instruction.
In the preferred embodiment, the control logic issues conditional GO signals that are executed only after the IDCT unit has finished processing. The conditional GO signals help the microcontroller to properly sequence the operations of the various decoding units. To facilitate the conditional GO instructions, the first multiplexer receives the output signal from the second multiplexer, i.e., a GO signal from either the GOFIFO or the default GO unit. The second multiplexer also receives an input signal that corresponds to a GO instruction for the variable length decoder. An AND gate receives a *COND_GO signal from the GOFIFO and also an inverted IDCT_RDY signal, providing an output signal to the control input terminal of the first multiplexer.
The output of the AND gate is asserted if the IDCT_RDY signal deasserted, indicating that the IDCT unit is processing, and if the *COND_GO signal is asserted, indicating that the dequeued signal represents a conditional GO instruction. If the AND gate output is asserted, then the first multiplexer transmits the GO signal corresponding to the variable length decoder, and the conditional GO instruction is delayed. When the IDCT unit finishes processing, as indicated by a deasserted IDCT_RDY signal, then the AND gate output signal will deassert, causing the first multiplexer to assert the GO signal corresponding to the conditional GO instruction. The conditional GO instruction is thereby delayed until the IDCT unit finishes processing. If the GOFIFO dequeues a GO instruction that is not conditional, then the *COND_GO signal causes the AND gate output to deassert, and the first multiplexer transmits the GO signal received from the GOFIFO. Accordingly, if the IDCT unit is not processing when the conditional GO instruction dequeues, then the first multiplexer will not delay asserting the conditional GO signal.